The modern trend in integrated circuit fabrication is to combine logic circuits and various memory elements in one chip. Respective devices for each of the different circuits on one chip optimally operate at different voltages. In addition, an integrated circuit on one chip is designed to accommodate multiple supply voltages.
Referring to FIG. 1, a cross sectional view of different devices on an integrated circuit chip is shown. A first MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 102, a second MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 104, and a third MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 108 are fabricated on a semiconductor wafer 107. The first MOSFET 102 is separated from the third MOSFET 106 by a first LOCOS (Local Oxidation on Substrate) region 108. The third MOSFET 106 is separated from the second MOSFET 104 by a second LOCOS (Local Oxidation on Substrate) region 110.
Referring to FIG. 2, a top view of the portion of the semiconductor wafer 107 holding the first MOSFET 102, the second MOSFET 104, and the third MOSFET 106 is shown. The cross sectional view of FIG. 1 is along a line A--A in the top view of FIG. 2.
The present invention is described with MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices having an oxide region as the gate terminal. However, the present invention may be applied to fabrication of any other type of device having an oxide region as part of that device.
Referring to FIG. 1, the first MOSFET 102 has a first oxide region 112 as the gate terminal of the first MOSFET 102, the second MOSFET 104 has a second oxide region 114 as the gate terminal of the second MOSFET 104, and the third MOSFET 106 has a third oxide region 116 as the gate terminal of the third MOSFET 106.
With the recent trend of combining logic circuits and various memory elements in one chip, different devices, such as MOSFETs, on a semiconductor wafer may be designed to operate with different voltages. Referring to FIG. 1, for example, a first thickness of the first oxide region 112 of the first MOSFET 102 is relatively thicker because the first MOSFET 102 is used to operate at a higher voltage. The first MOSFET 102 may be a high voltage MOSFET. A high voltage MOSFET is designed with a thicker gate oxide to resist voltage breakdown at high voltage operations.
A second thickness of the second oxide region 114 of the second MOSFET 104 is relatively thinner because the second MOSFET 104 is used to operate at lower voltage. The second MOSFET 104 may be a low voltage MOSFET. A low voltage MOSFET is designed with a thinner gate oxide to ensure that the low voltage MOSFET turns on even when a low voltage is applied on its gate terminal.
The third MOSFET 106 may be a tunnel device, and the third oxide region 116 in that case is amenable for the tunneling effect as known to one of ordinary skill in the art of transistor device design. In that case, the third thickness of the third oxide region 116 of the third MOSFET 106 is relatively thinner than the first thickness of the first oxide region 112 of the first MOSFET 102 but is relatively thicker than the second thickness of the second oxide region 114 of the second MOSFET 104.
With such diverse MOSFETs 102, 104, and 106 on one chip, a method for efficiently and effectively fabricating the oxide regions of various thicknesses is required. In the foreseeable future, the thickness of the thinnest oxide region on a semiconductor chip, for low voltage MOSFETs for example, may be just less than 30 .ANG. (angstroms) while the thickness of the thickest oxide region on that semiconductor chip, for high voltage MOSFETs for example, may be just less than 200 .ANG. (angstroms). In addition, intermediate thicknesses of devices, for tunnel MOSFETs for example, may be just less than 150 .ANG. (angstroms).
In the prior art, nitrogen implantation alone has been used to vary the thickness of oxide growth as discussed in the journal article, High Performance 0.2 .mu.m CMOS with 25 .ANG. Gate Oxide Grown on Nitrogen Implanted Si Substrates, by C.T. Liu et al., IEDM, 1996, pgs. 499-502. Nitrogen implantation before a thermal process of oxide growth results in inhibition of oxide growth. A larger dosage of nitrogen implantation results in thinner oxide regions. However, nitrogen implantation alone has limitations in the range of dosage that may be used to result in useful oxide regions. With excessive nitrogen implantation, the semiconductor wafer is damaged. Thus, nitrogen implantation alone has limits in the oxide thickness range which may be achieved.
In addition, in the prior art, oxygen implantation alone has been used to vary the thickness of oxide growth as discussed in the journal article, Sub-5 nm Multiple Thickness Gate Oxide Technology Using Oxygen Implantation, by Ya-Chin King et al., IEDM, 1998, pgs. 585-588. Oxygen implantation before a thermal process of oxide growth results in promotion of oxide growth. A larger dosage of nitrogen implantation results in thicker oxide regions. However, oxygen implantation alone has limitations in the range of dosage that may be used to result in useful oxide regions. With excessive oxygen implantation, the semiconductor wafer is damaged. Thus, oxygen implantation alone has limits in the oxide thickness range which may be achieved.
With the recent trend of combining more numerous different circuits on one chip, a wider range of oxide thicknesses than effectively achievable with nitrogen implantation alone or with oxygen implantation alone is desired. In addition, an efficient process for oxide growth which uses a minimized number of thermal processes is desired. A minimized number of thermal processes is more cost effective, less time-consuming, and may result in better circuit performance of the integrated circuit.